The present disclosure generally relates to via connections in semiconductor integrated circuits. More particularly, the present disclosure relates to artificially tilted via connections.
In conventional semiconductor integrated circuits, the spacing between two metal lines is typically small, and determined mainly in correspondence with the underlying via connections and design rule. Due to variations in the manufacturing process, such small spacings generally reduce yield or process margins by causing short circuits and/or reliability failures in a portion of the products.
In addition, the spacing between metal lines is further decreased as design rules are decreased. Thus, the lithography and Reactive Ion Etching (RIE) process margins are degraded. This further increases the possibility of shorts between neighboring lines, which generally leads to reliability failures, such as Time Dependent Dielectric Breakdown (TDDB).